搜索资源列表
16bit-Mulitiplier-Verilog-procedure
- 这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器-This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier
Multiplier
- 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
Serial-parallel-multiplier-verilog-design
- Serial parallel multiplier verilog design source code
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
verilog
- 最长的那个句子，求sum的赋值语句就是FIR滤波器的计算过程，将二进制乘法转化为移位运算。对于小数点后的乘数是向左移，小数点前的乘数是往右移位。 -The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the deci
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
Verilog-code-for-multiplier
- VERILOG CODE FOR 16 BIT MULTIPLIER USING MODIFIED BOOTH ALGORITHM
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
multiplier
- 4x4 multiplxer in verilog
32bit-multiplier-verilog
- 这是一个32位乘法器，是用verilog写的，比较详细-32*32 multiplier
some-kinds-multiple-Verilog
- 几种常见的乘法器的verilog代码，已经试过可用-some kinds of multiplier for verilog, it is useful
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
verilog-code-for-8bit-multiplier-using-vedic-algo
- The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
Array-multiplier
- Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
multiplier-by-verilog
- verilog写的浮点乘法器（原码一位乘法)-multiplier by verilog
polynominal-multiplier
- verilog code for polynominal multiplier